Memory chips comprise an array of memory cells which are interconnected by bit lines and word lines. The word lines and bit lines are used to read and write binary values to each of the memory cells. Each of the memory cells represents a bit of information. Since each memory cell represents a bit of information and may be connected to other circuitry, it is desirable that the electrical and operational characteristics of all memory cells be consistent.
The operational and electrical characteristics of memory cells vary depending on where a memory cell is located within a layout of the memory array. For example, memory cells along an edge of the memory array may have different electrical and operational characteristics than memory cells located in the inner region of the memory array. Therefore, a memory array may not have consistent electrical and operational characteristics throughout the memory chip.
In high density technologies (e.g., 7 nanometer technology or lower), each metal layer of a static random access memory (SRAM) is very resistive. Further, in the SRAM, a bit line (BL) is routed to a M0 metal layer (i.e., the lowest metal layer in the SRAM) for read and write operations. Therefore, a RC time constant (i.e., a time constant of a RC circuit which is a product of the RC circuit resistance and the RC circuit capacitance) of the bit line (BL) restricts a maximum number of cells per bit line (CPBL) of a memory bank in the SRAM. Further, after several read and write operations are performed, the RC time constant can degrade read and write cycle times. In particular, write operations are usually more sensitive than read operations because a bit line has higher read current than write current and relaxing a write line setting (WL-SET) for the read current can improve read operations.